Clock gating is a popular technique used in many synchronous circuits for reducing dynamic power dissipation. Clock gating generally saves power by adding more logic to a circuit to dynamically prune the clock tree. Dynamically pruning the clock tree often involves disabling portions of the circuitry so that the flip-flops or other synchronous devices in the execution units do not have to switch states. Switching states consumes power. When synchronous devices are prevented from or do not switch, the switching power consumption generally goes to zero, and only leakage currents are incurred.
Clock gating typically works by sending an enable signal to regional clock circuits, and using the enable signal to gate the clocks. This may be done by, for example, ANDing an inverted version of the enable and the global clock signal to generate the regional clock signal. If the enable signal indicates the clock should be disabled, the output of the AND gate will be low regardless of the state of the clock. Clock gating logic is generally manifested in the form of “integrated clock gating” (ICG) cells or circuits.
Traditionally, the ICGs make use of a latch to hold the value of the enable signal. This latch is traditionally controlled by the clock signal itself. This generally prevents the ICG from gating the clock midway through a clock cycle, which would result in a glitch. However, it also means that the ICG consumes switching power even when the regional clock is being gated, as the global or ungated clock is switching the latch portion of the ICG.